Digital/ASIC/FPGA circuit design experience includes: Embedded Microprocessor, Microcontroller, and DSP interface and memory support circuitry; state machines, parallel, serial, and telecommunications circuitry, encoding and decoding blocks, analog/digital interface and conversion circuitry (ADC/DAC); Experienced in the design of Digital Phase Locked Loops for frequency synthesis up to 38 GHz - Integer-N and Fractional-N loops with IF frequencies inside the FPGA up to 200MHz; Telecom Optical Carrier/SDH/PDH, DMS/Time Division Multiplexing/Timeswitching, PRBS generation/detection, and ISDN interfaces.

Extensive experience using VHDL and VERILOG as well as logic synthesis tools like SYNOPSYS, SYNPLIFY, LEONARDO SPECTRUM, and PRECISION RTL in the design and development of ASICs and FPGAs. Extensive ASIC/FPGA design, verification, and testbench development experience. C & PERL used for design validation in the simulation environment. Experienced with the MENTOR toolset. Have used a variety of schematic capture packages such as VIEWLOGIC and ORCAD. Designs realized using discrete components, PLD’s, FPGA’s such as ACTEL, XILINX, QUICKLOGIC, ATMEL, CYPRESS, LATTICE and standard cell CMOS Gate Array/ASIC’s such as Honeywell and Mitsubishi.

Analog/RF Circuit Experience

Analog circuit design experience includes: Synchronous & Asynchronous feedback control circuits, high voltage switch-mode power supplies, power regulation/ monitoring circuits, audio frequency processing, routing and multiplexing circuitry; Microwave Frequency Synthesis using DPLL techniques - Integer-N and Fractional-N loops with IF frequencies inside the FPGA up to 200MHz and output frequencies up to 38 GHz, using OTS VCOs, ECL and GaAs dividers, prescalers, and mixers. Touchstone and the Super-Compact family of RF tools used for Discrete, Hybrid and MMIC circuit design and simulation. Extensive analog simulation experience using Pspice, Analog Workbench and others for component modeling, concept creation, design verification, and worst case analysis.

Experience gained in 16 years as an Electrical Engineer with such companies as Honeywell's Space and Strategic Systems Operations, Sundstrand Aerospace, Digital Lightwave, Trak Microwave, Hamilton Sundstrand, Northern Telecom/Bell Northern Research, BF Goodrich Aerospace and Square D. Also 12 years as an FCC Amateur Extra Class Licensee and 4 years as an Aircraft Maintenance Specialist in the United States Air Force.

Active Security Clearance
BSEE & MSEE, University of South Florida, Tampa, Florida

03/2002 to 5/2004;
Hamilton Sundstrand, Windsor Locks, Connecticut
Digital Electronic Engine Control And Health Monitor Design. DSP bus control, direct memory access and arbitration, multiple high speed ADC control for data collection, DAC control, and UART & SPORT Port implementations for communication. Four DSPs & a PPC interfaced to 10 ADCs, a DAC, and a programmable RF filter.
MODELSIM, LEONARDO, PRECISION RTL, FPGA ADVANTAGE, AD7895, AD7671, AD7243, LTC1564, 600,000 + gates, ACTEL PRO-ASIC PLUS (FPGA-VHDL)

02/2000 to 8/2001;
Digital Lightwave, Clearwater, Florida
Optical Carrier Telecom Test Equipment Design. SDH/SONET, AU3/4/4-4c pointer generation, processing, movement, and termination. ATM insertion and PRBS generation/detection. STS1/STM0,STS3-3c/STM1,STS12-12c/STM4, OC-1,OC-3,OC-12, OC-48,OC-192. PMC Sierra PM5312 and PM5344 interfaces.
MODELSIM, SYNPLIFY, LUCENT-ORCA (FPGA-VHDL)

05/1999 to 10/2001;
Sundstrand Aerospace, Rockford, Illinois
Processor Interfaces and large multi-state machine designs, (15 plus inter-dependent state machines), provided the circuit troubleshooting, power routing/switching, and DC bus protection/isolation of complete aircraft DC power systems via Solid State Power Controllers.
CADENCE-LEAPFROG, MODELSIM,VERIBEST, SYNPLIFY, VIEWLOGIC, ACTEL.(FPGA-VHDL)

02/1998 to 05/1999;
Trak Microwave, Tampa Florida
Processor Interfaces, state machines, parallel and serial data communications circuitry, encoding and decoding blocks, analog/digital interface and circuit board design, and Digital Phase Locked Loops for microwave frequency synthesizers up to 38 GHz. GPS system integration.
MODELSIM, SYNPLIFY, EAGLEWARE, SUPER-COMPACT, ACTEL, QUICKLOGIC, XILINX.(FPGA-VHDL, Spice)

07/1996 to 02/1998;
Northern Telecom, Research Triangle Park, North Carolina
Processor interfaces, parallel and serial data communications circuitry, encoding and decoding blocks; Telecom DMS/Time Division Multiplexing, Timeswitching and POTS/ISDN interface functions. Large scale testbench and verification suites - code coverage test suites and Hardware Modelers.
CADENCE VERILOG-XL/NC, PERL, SYNOPSYS, VERICOV, ALTERA, Mitsubishi ASICs. (ASIC/FPGA-VERILOG)

12/1995 to 07/1996;
Square-D Corporation, Knightdale, North Carolina
Parallel and serial data communications circuitry, state machines, encoding and decoding blocks, analog/digital interface and conversion circuitry (ADC/DAC) and circuit board design to interface an ASIC to a very long serial data bus system used to control factory assembly lines.
(FPGA/CPLD-ABEL HDL & VHDL)

01/1988 to 7/1995;
Honeywell Space And Strategic Systems Operations, Clearwater Florida
Embedded Microprocessor, Microcontroller, and DSP interface and memory support circuitry; state machines, parallel and serial data communications circuitry, encoding and decoding blocks, analog/digital interface and conversion circuitry for Inertial Guidance and Navigation Systems for Inertial Upper Stages and Satellite Control. Board/system level testbenches including Hardware Modelers. Analog circuit design, verification and analysis.
VANTAGE, SYNOPSYS, MENTOR GRAPHICS, HSC, ACTEL, XILINX. (ASIC & FPGA-VHDL-Spice)